The present invention relates to chip design, and more specifically, to hierarchical wire-pin co-optimization.
Part of the process of obtaining a physical implementation of a chip design involves pin placement. Pin (or wire-pin) placement is part of the physical synthesis step in chip design. A chip is typically organized hierarchically. Each portion of the design hierarchy (referred to as a block or unit) includes a number of sub-blocks (referred to as macros). Each unit and each macro include a number of layers of metal. Each of the layers includes wires, and the pins are interfaces for wires to go between macros. In addition, macro-level pins are assigned locations defined by three perpendicular axes since the pins may be allocated on different levels or metal layers. Currently, each macro is assigned pin locations for its interior pins by a unit-level controller. These assignments stem from a chip-level controller that assigns pin locations to each unit.